Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/NXP Semiconductors/NeoM3/GPDMA/LLI3#0x0
DMA Channel 0 Linked List Item Register
Reserved, and must be written as 0.
Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
https://github.com/cmsis-svd/cmsis-svd-data